Senior Staff Design Verification Engineer – Coherent Interconnect

About SiFive The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.

SiFive

S

sifive.com

501-1,000 employees

Semiconductor Manufacturing

Santa Clara, California

Privately Held

66k LinkedIn followers

Raised $765.5M

• SiFive is looking for a Senior Staff Design Verification Engineer to lead
• verification of a next-generation cache-coherent interconnect subsystem used in
• high-performance SoCs.
• verification strategy, identifying risk early, solving complex subsystem-level
• problems, and raising the quality bar across the broader verification effort.
• In this role, you will work across architecture, RTL, formal, and design
• verification teams to verify coherent data movement, protocol correctness,
• ordering, flow control, quality-of-service behavior, and subsystem integration
• across multiple interfaces and bridge paths.
• interconnect subsystem, from block-level verification through subsystem
• integration and signoff.
• Define verification strategy, test plans, environments, and closure criteria
• for coherent traffic, ordering rules, backpressure, flow control, buffering
• behavior, QoS, and error handling.
• Develop and maintain robust verification environments, checkers, scoreboards,
• assertions, stimulus, and coverage models to validate complex interconnect
• and protocol behavior.
• Drive verification of subsystem behavior across interface boundaries,
• protocol adaptation layers, and bridge paths, including CHI, ACE, CXL, and
• related coherent interconnect flows.
• Create high-value directed and constrained-random scenarios that expose
• corner cases in coherency, concurrency, credits, arbitration, QoS, and
• bandwidth-sensitive behavior.
• Partner closely with architecture, RTL, formal, and software teams to review
• specifications, close ambiguities early, and improve overall verification
• quality.
• Debug failures efficiently, isolate root cause, and drive fixes across RTL,
• assertions, testbench infrastructure, and test content.
• Contribute to methodology and infrastructure improvements that benefit the
• broader horizontal interconnect verification effort, not just the block
• directly assigned to you.
• Mentor engineers and help raise verification quality across the team.
• architectural risks.
• durable fixes.
• Coverage and test quality improve meaningfully under your ownership.
• The coherent interconnect verification effort becomes more scalable,
• predictable, and reusable because of your contributions.
• Design and architecture teams rely on you as a strong technical partner for
• difficult verification and debug problems.
• You will be part of a high performance Out-of-Order Core team that focuses on
• verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer
• and Floating Execution Unit, as well as Vector Unit that implement the latest
• RVV.
• 8+ years relevant experience with IP/Component functional verification,
• preferably in Core/CPU verification
• Seasoned developer using object oriented programing principles
• In addition to base pay, this role may be eligible for variable/ incentive
• compensation and/ or equity.  In addition, this role is eligible for a
• comprehensive, competitive benefits package which may include healthcare and
• retirement plans, paid time off, and more!

Required

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science,
• or a related field.
• appropriate for a Senior Staff / T5 role.
• verification infrastructure for complex hardware subsystems.
• Strong understanding of cache-coherent systems, on-chip interconnects, memory
• subsystem behavior, and verification of ordering and flow-control semantics.
• Strong protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent and
• high-performance interconnect standards.
• workflows for complex hardware subsystems.
• Strong scripting and automation skills in Python or similar languages.
• architecture, RTL, and verification teams in a fast-moving environment.

Preferred

• Experience verifying coherent interconnect, cache, or memory-subsystem IP in
• high-performance SoCs.
• Experience with protocol-conversion or bridge-heavy subsystems.
• Experience with formal verification, performance-oriented verification, or
• emulation / FPGA-assisted debug.
• Demonstrated technical leadership and the ability to influence verification
• quality beyond immediate ownership.

• Healthcare
• Retirement Plans
• Paid Time Off
• Variable/Incentive Compensation
• Equity