Principal Embedded Firmware Engineer — AI/HPC Networking Silicon

About Cornelis Networks, Inc. Cornelis is solving one of the world’s biggest compute efficiency challenges—unlocking application performance with network-led acceleration at any scale. Built on the proven Omni-Path architecture, Cornelis is the only open fabric architecture that spans scale-up and scale-out, turning the network from passive transport into an active compute layer that drives faster AI and HPC outcomes.

Cornelis Networks, Inc.

Deliver the network performance your AI hardware was built for

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C

cornelisnetworks.com

201-500 employees

Computer Networking Products

Wayne, PA

2020

Privately Held

16k LinkedIn followers

Raised $410.3M

• Architect and implement bare-metal C firmware on a RISC-V management core that provisions, boots, and supervises arrays of on-chip acceleration engines.
• Own the secure firmware-loading pipeline: fetch images from flash, coordinate hardware root-of-trust authentication, and distribute verified images into each engine's local memories through on-chip fan-out/DMA hardware.
• Build per-engine bring-up, reset sequencing, and health validation driven by control/status registers, with solid
• timeout and error handling and enforced security invariants.
• Scale firmware distribution and bring-up across many engines and multiple dies, including runtime re-boot and in-field firmware updates.
• Define the hardware/software contract with ASIC/RTL teams using a datamodel-first workflow (e.g., SystemRDL, Kaitai, YAML → generated code).
• Validate firmware against functional simulators (e.g., QEMU) with automated unit and integration tests.
• Set architecture standards, review designs and code, and mentor engineers.

Required

• 10+ years of embedded/firmware engineering, with a track record of software architecture and technical leadership.
• Expert C (C++ a plus) and working Python.
• Deep experience with bare-metal firmware on constrained cores, including manually managed local memories and low level bring-up.
• Experience with secure boot / image authentication and hardware root-of-trust integration.
• Experience programming hardware CSRs and co-designing register-level interfaces with silicon teams.
• Demonstrated, hands-on AI-assisted engineering proficiency, plus the judgment to validate what the AI produces.

Preferred

• RISC-V firmware and toolchain experience.
• Firmware orchestration for multi-core accelerator arrays.
• Hardware root-of-trust ecosystems (e.g., Caliptra) and SHA-2/signature verification.
• Code-generation toolchains (SystemRDL, Kaitai, CMake) and simulator-based co-verification.
• Familiarity with emerging AI/HPC interconnect standards: Ultra Ethernet (UEC), UALink, and ESUN.
• Background in HPC/AI networking, RDMA, or libfabric.

• Health Insurance
• Dental Coverage
• Vision Coverage
• Disability Insurance
• Life Insurance
• Dependent Care Flexible Spending Account
• Accidental Injury Insurance
• Pet Insurance
• Paid Holidays
• 401(k) with Company Match
• Open Time Off
• Sick Time
• Bonding Leave
• Pregnancy Disability Leave
• Equity
• Performance-based Incentives